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| the mark h shows major revised points. 8-bit single-chip microcomputer (with a/d converter) mos integrated circuit data sheet the information in this document is subject to change without notice. data sheet document no. ic-2678c (o. d. no. ic-7769e) date published february 1995 p printed in japan description the m pd78c11a is a cmos 8-bit microprocessor which can integrate 16-bit alu, rom, ram, an a/d converter, a multi-function timer/event counter, and a general-purpose serial interface into a single chip, then expand the memory (rom/ram) up to 60k bytes externally. the m pd78c10a is a rom-less product of the m pd78c11a, and can directly address the external memory up to 64k bytes. the m pd78c12a is a product which has more built-in rom capacity than the m pd78c11a, and its memory (rom/ram) can be externally extended up to 56k bytes. the m pd78c10a, m pd78c11a, and m pd78c12a operated at low power consumption, because they have a cmos construction. also, they can hold data with low power consumption by using standby function. on-chip prom products, m pd78cp14 and m pd78cp18 which are ideal for evaluation or preproduction use during system development, early start-up and short-run multiple-device production of application sets, are available. features abundant 159 types of instructions : 87ad series instruction set, multiplication/division instructions, 16-bit operation instructions instruction cycle : 0.8 m s (at 15 mhz operation) on-chip rom : 4096w 8 ( m pd78c11a), 8192w 8 ( m pd78c12a) non ( m pd78c10a) on-chip ram : 256w 8 high-precision 8-bit a/d converter : 8 analog inputs general-purpose serial interface : asynchronous, synchronous, i/o interface mode multi-function 16-bit timer/event counter two 8-bit timers i/o lines : 32 ( m pd78c10a), 44 ( m pd78c11a, 78c12a) interrupt function (external - 3, internal - 8) : non-maskable interrupt 1, maskable interrupt 10 standby function : halt mode, hardware/software stop mode zero-cross detection function : (2 inputs) on-chip pull-up resistor (port a, b, c: m pd78c11a, 78c12a only) by mask option caution the m pd78c10a does not hava a mask option. m pd78c10a, 78c11a, 78c12a 1990
2 m pd78c10a,78c11a,78c12a ordering information ordering code package on-chip rom m pd78c10acw 64-pin plastic shrink dip (750 mil) none m pd78c10agf-3be 64-pin plastic qfp (14 20 mm) none m pd78c10agq-36 64-pin plastic quip none m pd78c10al 68-pin plastic qfj ( 950 mil) none m pd78c11acw- 64-pin plastic shirink dip (750 mil) mask rom m pd78c11agf- -3be 64-pin plastic qfp (14 20 mm) mask rom m pd78c11agq- -36 64-pin plastic quip mask rom m pd78c11agq- -37 64-pin plastic quip straight mask rom m pd78c11al- 68-pin plastic qfj ( 950 mil) mask rom m pd78c12acw- 64-pin plastic shrink dip (750 mil) mask rom m pd78c12agf- -3be 64-pin plastic qfp (14 20 mm) mask rom m pd78c12agq- -36 64-pin plastic quip mask rom m pd78c12agq- -37 64-pin plastic quip straight mask rom m pd78c12al- 68-pin plastic qfj ( 950 mil) mask rom 3 m pd78c10a,78c11a,78c12a m pin configuration (top view) for m pd78c10acw, m pd78c10agq-36, m pd78c11acw- , m pd78c11agq- -36/37, m pd78c12acw- , m pd78c12agq- -36/37. for m pd78c10agf-3be, m pd78c11agf- -3be, m pd78c12agf- -3be an4 an3 an2 an1 an0 av ss v ss x1 x2 mode0 reset mode1 int1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 pa0 pa1 pd3 pd4 pd5 pd6 pd7 stop v dd pa2 pa3 pa4 pa5 45678910111213141516171819 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 pf7 pf6 pf5 pf4 51 50 49 123 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 pc4/to pc5/ci pc6/co0 pc7/co1 nm1 pa6 pa7 pb0 pd2 pd1 pd0 1 pa0 2 pa1 3 pa2 4 pa3 5 pa4 6 pa5 7 pa6 8 pa7 9 pb0 10 pb1 11 pb2 12 pb3 13 pb4 14 pb5 15 pb6 16 pb7 17 pc0/t x d 18 pc1/r x d 19 pc2/sck 20 pc3/int2 21 pc4/to 22 pc5/ci 23 pc6/co0 24 pc7/co1 25 nmi 26 int1 27 mode1 28 reset 29 mode0 30 x2 31 x1 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd v aref an7 an6 an5 an4 an3 an2 an1 an0 av ss 4 m pd78c10a,78c11a,78c12a for m pd78c10al, m pd78c11al- , m pd78c12al- ic pa6 pa5 pa4 pa3 pa2 pa1 pa0 v dd stop pd7 pd6 pd5 pd4 pd3 pd2 ic pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0/t x d pc1/r x d pc2/sck pc3/int2 ic pc4/to pc5/ci pc6/co0 pd1 pd0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 ale wr rd av dd ic v aref an7 9876543216867666564636261 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pc7/c01 nmi int1 mode1 reset mode0 x2 x1 v ss av ss an0 an1 an2 an3 an4 an5 an6 5 m pd78c10a,78c11a,78c12a serial i/o x1 alu (8/16) pc0/t x d x2 pc1/r x d pc2/sck osc int. control nmi int1 8 8 4 8 timer timer/ event counter 8 8 8 pc3/int2/ti pc4/to pc5/ci pc6/co0 pc7/co1 a/d converter v aref av dd av ss 8 latch inc/dec pc sp ea ea' va bc de hl v' a' b' c' d' e' h' l' buffer 8 16 12/ 13 program *1 memory data memory (256-byte) 8/16 inst.reg latch latch 16 16 internal data bus 16 16 16 6 inst. decoder 8 8 stand by control system control read/write control reset v ss v dd stop mode0 mode1 ale wr rd port f 8 8 8 port d 8 8 8 port c 8 pc7-0 *2 8 port b 8 pb7-0 *2 8 port a 8 pa7-0 *2 8 16 an7-0 psw pd7-0/ ad7-0 pf7-0/ ab15-8 main g.r alt g.r 8 8 block diagram *1. it depends on a product type. the m pd78c11a has 4k bytes, and the m pd78c12a has 8k bytes. the m pd78c10a does not incorporate a program memory. 2. an on-chip pull-up resistor is available by mask option ( m pd78c11a, 78c12a only). 6 m pd78c10a,78c11a,78c12a contents 1. pin functions ............................................................................................................................... ...... 7 1.1 list of pin function ............................................................................................................................... .7 1.2 pin input/output circuits .................................................................................................................... 9 1.3 pin mask options ............................................................................................................................... ....... 14 1.4 recommended connection of unused pins .................................................................................. 14 2. differences between m pd78c10a and m pd78c11a, 78c12a ................................................... 15 3. reset operations ............................................................................................................................. 17 4. instruction set ............................................................................................................................... .. 20 4.1 identifier/description of operand ................................................................................................... 20 4.2 symbol description of operation code ......................................................................................... 21 4.3 instruction execution time ................................................................................................................ 22 5. list of mode registers .................................................................................................................. 34 6. electrical specifications ............................................................................................................. 35 7. characteristic curves (reference values) ......................................................................... 47 8. differences in 87ad series products ...................................................................................... 50 9. package information ..................................................................................................................... 54 10. recommended soldering conditions ...................................................................................... 60 appendix development tools ............................................................................................................ 62 7 m pd78c10a,78c11a,78c12a strobe signal to latch externally the lower address information which is output to pd7 to pd0 pins to access external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. strobe signal which is output for write operation of external memory. it becomes high in any cycle other than the data write machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. strobe signal which is output for read operation of external memory. it becomes high in any cycle other than the read machine cycle of external memory. when reset signal is either low or in the hardware stop mode, this signal becomes output high-impedance. 1. pin functions 1.1 list of pin function (1/2) function pin name i/o pb7 to pb0 (port b) receive data input pin for serial data. input-output/ input transmit data output pin for serial data. serial clock input-output pin for serial clock. it becomes output clock for the internal clock use, and input for the external. interrupt request/timer input maskable interrut input pin of the edge trigger (falling edge), or an external clock input pin for a timer. also, it can be used as a zero-cross detection pin for ac input. timer output square wave defining one cycle of internal clock or timer counter time as half cycle is output. counter input external pulse input pin to timer/event counter. counter output 0, 1 programmable rectangle wave output by timer/event counter. address/data bus when external memory is used, it be- comes multiplexed address/data bus. port d 8-bit input-output port, which can specify input-output in byte units ( m pd78c11a). port f 8-bit input-output port, which can specify input-output bit-wise. address bus when external memory is used, it be- comes address bus. port c 8-bit input-output port, which can specify input/ output bit-wise. pa7 to pa0 (port a) 8-bit input-output port, which can specify input/output bit-wise. 8-bit input-output port, which can specify input/output bit-wise. input/output input/output input-output/ output pc0/t x d pc1/rxd pc2/sck input-output/ input-output pc3/int2/ti input-output/ input/input input-output/ output pc4/to pc5/ci input-output/ input pc6/co0 pc7/co1 input-output/ output pd7 to pd0/ ad7 to ad0 input-output/ input-output pf7 to pf0/ ab15 to ab8 input-output/ output wr (write strobe) output rd (read strobe) output ale (address latch enable) output 8 m pd78c10a,78c11a,78c12a m pd78c11a and 78c12a sets mode0 pin to 0 (low level), and mode1 pin to 1 (high level * ) m pd78c10a allows you to set mode0, mode1 pins to select 4k, 16k, or 64k bytes for the size of the memory which is installed externally. mode0 mode1 external memory 0 0 4k bytes 1 0 16k bytes 1 1 64k bytes also, when each of mode0 and mode1 pins is set to 1 * , it is synchronized to ale to output a control signal. 1.1 list of pin function (2/2) function pin name i/o input-output mode0 mode1 (mode) input control signal input pin in hardware stop mode. the oscillation stops when a clock is supplied from outside. 8 pins of analog input to a/d converter. an7 to an4 can be used as edge detection (falling edge) input. * pull-up. pull-up resister r is 4 [k w ] r 0.4 t cyc [k w ] (t cyc is ns unit). remarks the m pd78c11a and m pd78c12a are pull-up resistor incorporation specifiable by mask option at ports a, b and c. nmi (non-maskable interrupt) int1 (interrupt request) input non-maskable interrupt input pin of the edge trigger (falling edge) a maskable interrupt input pin of the edge trigger (rising edge). also, it can be used as a zero-cross detection pin for ac input. input an7 to an0 (analog input) v aref (reference voltage) input a common pin serving both as a standard voltage input pin for a/d converter and as a control pin for a/d converter operation. av dd (analog v dd ) power supply pin for a/d converter. av ss (analog v ss ) gnd pin for a/d converter. x1, x2 (crystal) reset (reset) stop (stop) v dd v ss crystal connection pins for system clock oscillation. x1 should be input when a clock is supplied from outside. input the clock of the reverse phase of x1 to x2. input low-level active system reset input. positive power supply pin. gnd pin. h 9 m pd78c10a,78c11a,78c12a pa7 to pa0 5 reset 2 pb7 to pb0 5 rd 4 pc1 to pc0 5 wr 4 pc2/sck 8 ale 4 pc3/int2 10 stop 2 pc7 to pc4 5 mode0 11 pd7 to pd0 5 mode1 11 pf7 to pf0 5 an3 to an0 7 nmi 5 an7 to an4 12 int1 2 v aref 13 pin name pin name type no. type no. table 1-2 pin type no. ( m pd78c11a and 78c12a) pa7 to pa0 5-a reset 2 pb7 to pb0 5-a rd 4 pc1 to pc0 5-a wr 4 pc2/sck 8-a ale 4 pc3/int2 10-a stop 2 pc7 to pc4 5-a mode0 11 pd7 to pd0 5 mode1 11 pf7 to pf0 5 an3 to an0 7 nmi 2 an7 to an4 12 int1 9 v aref 13 pin name pin name type no. type no. 1.2 pin input/output circuits tables 1-1 and 1-2, and figures (1) to (15) show input- output circuits of each pin in a partially simplified form. table 1-1 pin type no. ( m pd78c10a) 10 m pd78c10a,78c11a,78c12a (1) type 1 (2) type 2 (3) type 4 (4) type 4-a v p-ch output disable n-ch out dd output data p-ch output disable n-ch out v dd output data v dd p- in n- ch ch in 11 m pd78c10a,78c11a,78c12a (5) type 5 (6) type 5-a (7) type 7 (8) type 8 type5 type2 output data output disable in/out mcc in/out output data output disable type4 type1 in/out output data output disable type4-a type1 p-ch n-ch av dd av dd av ss sampling c + - reference voltage (from voltage tap of series resistance string) in av ss 12 m pd78c10a,78c11a,78c12a (9) type 8-a (10) type 9 (11) type 10 type1 in self bias enable data type5 type9 output data output disable in/out mcc self bias enable type5-a type2 output data output disable in/out mcc 13 m pd78c10a,78c11a,78c12a (12) type 10-a (13) type 11 (14) type 12 (15) type 13 type5-a type9 output data output disable in/out mcc self bias enable type1 n-ch output data in/out in type7 type2 edge detector type1 in av ss stop mode 14 m pd78c10a,78c11a,78c12a pa7 to pa0 pb7 to pb0 pc7 to pc0 pd7 to pd0 pf7 to pf0 rd wr ale stop int1, nmi av dd av aref av ss an7 to an0 1.3 pin mask options m pd78c11a and 78c12a has the following mask options, which can be selected bit-wise according to the application. cautions 1. zero-cross function can not be operated normally if pull-up resistor is incorporated in pc3. 2. m pd78c10a has no mask option. pin name mask options pa7 to pa0 pb7 to pb0 pc7 to pc0 pull-up resistor incorporated pull-up resistor not incorporated 1.4 recommended connection of unused pins recommended connection pin connect to v ss or v dd via resistor leave open connect to av ss or av dd connect to v dd connect to v ss or v dd connect to v dd connect to v ss 15 m pd78c10a,78c11a,78c12a pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 external memory port port port port port port port port maximam 256 bytes port port port port ab11 ab10 ab9 ab8 maximum 4k bytes port port ab13 ab12 ab11 ab10 ab9 ab8 maximum 16k bytes ab15 ab14 ab13 ab12 ab11 ab10 ab9 ab8 maximum 56k/60k bytes * external memory is accessed by using pd7 to pd0 (multiplexed address/data bus), pf7 to pf0 (address bus), and the rd, wr, and ale signals. when 4k-byte or 16k-byte external memory is accessed pf7 to pf0 not used as address lines can be used as general purpose input/output ports. the size of external memory can be specified by mode0 and mode1 pin setting. preset each bit of memory mapping reisters mm2, mm1, and mm0 to "0". (2) m pd78c11a and 78c12a the m pd78c11a has an on-chip mask programmable rom at addresses 0000h to 0fffh and ram at addresses ff00h to ffffh. externally, memory can be extended up to 60k bytes (addresses 1000h to feffh) in steps. the m pd78c12a has an on-chip mask programmable rom at address 0000h to 1fffh and ram at address ff00h to ffffh. externally, memory can be extended up to 56k bytes (address 2000h to feffh) in steps. the size of the external extension memory can be selected from among no external memory, 256 bytes, 4k bytes, 16k bytes, and 56k/60k bytes * by memory mapping register setting. external memory can be accessed by using pd7 to pd0 (multiplexed address/data bus), pf7 to pf0 (address bus), and the rd, wr, and ale signals. programs and data can be stored in external memory. pf7 to pf0 become address lines corresponding to the size of external memory. the remaining pins can be used as general purpose input/output ports. 2. differences between m pd78c10a and m pd78c11a, 78c12a the difference between the m pd78c10a and m pd78c11a, 78c12a is whether or not there is an on-chip mask programmable rom. the memory map differs accordingly as described below. (1) m pd78c10a since the m pd78c10a does not have an on-chip rom, all memory, except the on-chip ram area (addresses ff00h to ffffh) can be installed outside. the size of this external memory can be selected from among 4k bytes (0000h to 0fffh), 16k bytes (0000h to 3fffh), and 64k bytes (0000h to feffh) by mode0 and mode1 pin setting as shown in the following table and fig. 2-1. 4k bytes access 16k bytes access 64k bytes access mode1 0 0 1 mode0 0 1 1 4k bytes (address 0000h to 0fffh) 16k bytes (address 0000h to 3fffh) 64k bytes (address 0000h to feffh) address ff00h to ffffh address ff00h to ffffh address ff00h to ffffh control pin operation mode external memory on-chip ram * m pd78c11a: 60k bytes, m pd78c12a: 56k bytes 16 m pd78c10a,78c11a,78c12a fig. 2-1 m pd78c10a memory map not used not used ffffh ff00h 0000h 0fffh 3fffh 4k bytes access 16k bytes access 64k bytes access mode0 = 1 mode1 = 1 mode0 = 1 mode1 = 0 mode0 = 0 mode1 = 0 a b c j k l 1 2 3 : ; < c d e l m n " # + , 4 5 = > f g o p external memory on-chip ram external memory on-chip ram external memory on-chip ram 17 m pd78c10a,78c11a,78c12a 3. reset operations when reset input becomes low, the system reset is activated to create the following status. interrupt enable f/f is reset and interrupt is disabled. all the interrupt mask registers are set (1) and interrupt is masked. an interrupt request flag is reset (0) and hold interrupt is eliminated. each bit of psw is reset (0). 0000h is loaded into the program counter (pc). the mode a, mode b, mode c, and mode f registers are set to ffh and the bits (mm0, 1, and 2) of the mode control c and memory mapping registers are respectively reset (0), then all the ports (a, b, c, d, and f) become input port (output high-impedance). all the test flags but sb flag are reset (0). a timer mode register is set to ffh, and timer f/f is reset. the mode register (etmm, eom) of a timer/event counter is reset (0). the serial mode high register(smh) of serial interface is reset (0), while the serial mode low register (sml) is set to 48h. the a/d channel mode register of the a/d converter is reset (0). wr, rd, ale signals become high-impedance. the zc1, zc2 bits of the zero-cross mode register (zcm) are set (1). the internal timing generator is initialized. data memory and the following register contents are undefined: stack pointer (sp) expansion accumulator (ea, ea), accumulator (a, a) general register (b, c, d, e, h, l, b, c, d, e, h, l) output latch of each port timer reg0, 1 (tm0, tm1) timer/event counter reg0, 1 (etm0, etm1) rae bit of memory mapping register sb flag of test flag when reset input becomes high, the reset status is released. then, execution of the program is started from 0000h. the contents of various kinds of registers must be initialized or re-initialized in the program, if necessary. table 3-1 shows the state of each hardware after reset. table 3-2 shows the state of each pin after reset. 18 m pd78c10a,78c11a,78c12a ffh 0 undefined timer mode register (tmm) timer timer f/f timer register (tm0, tm1) timer/event counter mode register (etmm) timer/event counter output mode register (eom) timer/event counter timer/event counter register (etm0, etm1) timer/event counter capture register (ecpt) timer/event counter (ecnt) serial mode high register (smh) serial mode low register (sml) a/d channel mode register (anm) mm register (mm3; rae bit) zero cross mode register (zc1, zc2 bits) table 3-1 state of each hardware after reset expansion accumulator (ea, ea') accumulator (a, a') general register (b, c, d, e, h, l, b', c', d', e', h', l') working register vector register (v, v') program counter (pc) stack pointer (sp) mode register (ma, mb, mc, mf) port mcc register mm register (bits mm0 to mm2) output latch of each port interrupt enable f/f interrupt request flag mask register test flag (except sb flag) power-on reset standby flag (sb) standby mode hardware reset input during normal operation internal data memory 0000h undefined ffh 00h 0 undefined 0 0 ffh 0 1 previous contents held. contents immediately before reset input held 00h undefined 00h 48h 00h undefined 1 undefined serial interface state after reset reset input during normal operation reset input in standby mode writing by cpu write address data address data other than the aboove power-on reset previous contents held. undefined previous contents held. operation other than writing by cpu 19 m pd78c10a,78c11a,78c12a wr rd ale all ports (pa, pb, pc, pd, pf) high-impedance state after reset pin table 3-2 state of each pin after reset 20 m pd78c10a,78c11a,78c12a identifier description r v, a, b, c, d, e, h, l r1 eah, eal, b, c, d, e, h, l r2 a, b, c sr pa, pb, pc, pd, pf, mkh, mkl, anm, smh, sml, eom, etmm, tmm, mm, mcc, ma, mb, mc, mf, txb, tm0, tm1, zcm sr1 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm, rxb, cr0, cr1, cr2, cr3 sr2 pa, pb, pc, pd, pf, mkh, mkl, anm, smh, eom, tmm sr3 etm0, etm1 sr4 ecnt, ecpt rp sp, b, d, h rp1 v, b, d, h, ea rp2 sp, b, d, h, ea rp3 b, d, h rpa b, d, h, d+, h+, dC, hC rpa1 b, d, h rpa2 b, d, h, d+, h+, dC, hC, d+byte, h+a, h+b, h+ea, h+byte rpa3 d, h, d++, h++, d+byte, h+a, h+b, h+ea, h+byte wa 8 bit immediate data word 16 bit immediate data byte 8 bit immediate data bit 3 bit immediate data f cy, hc, z irf nmi * , ft0, ft1, f1, f2, fe0, fe1, fein, fad, fsr, fst, er, ov, an4, an5, an6, an7, sb remarks 1. sr to sr4 (special register) 2. rp to rp3 (register pair) 4. f (flag) pa : port a etmm : timer/event pb : port b counter mode pc : port c eom : timer/event pd : port d counter output pf : port f mode ma : mode a anm : a/d channel mode mb : mode b cr0 : a/d conversion mc : mode c to result 0 to 3 mcc : mode control c cr3 mf : mode f txb : t x buffer mm : memory mapping rxb : r x buffer tm0 : timer reg0 smh : serial mode high tm1 : timer reg1 sml : serial mode low tmm : timer mode mkh : mask high etm0 : timer/event mkl : mask low counter reg0 zcm : zero cross mode etm1 : timer/event counter reg1 ecnt : timer/event counter upcounter ecpt : timer/event counter capture sp : stack pointer b:bc d:de h:hl v:va ea : extended accumulator 3. rpa to rpa3 (rp addressing) b : (bc) d : (de) h : (hl) d+ : (de)+ h+ : (hl)+ dC : (de)C hC : (hl)C d++ : (de)++ h++ : (hl)++ d + byte : (de + byte) h + a : (hl + a) h + b : (hl + b) h + ea : (hl + ea) h + byte : (hl + byte) nmi : nmi input ft0 : intft0 ft1 : intft1 f1 : intf1 f2 : intf2 fe0 : intfe0 fe1 : intfe1 fein : intfein fad : intfad fsr : intfsr fst : intfst er : error ov : overflow an4 : analog input 4 to 7 to an7 sb : standby cy : carry hc : half carry z : zero 5. irf (interrupt flag) 4. instruction set 4.1 identifier/description of operand * nmi can also be described as fnmi. 21 m pd78c10a,78c11a,78c12a 4.2 symbol description of operation code r 2 0 0 0 0 1 1 1 1 r 1 0 0 1 1 0 0 1 1 r 0 0 1 0 1 0 1 0 1 reg v a b c d e h l s 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 s 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 s 3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 s 2 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 s 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 s 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 special-reg pa pb pc pd pf mkh mkl anm smh sml eom etmm tmm mm mcc ma mb mc mf txb rxb tm0 tm1 cr0 cr1 cr2 cr3 zcm rr1 sr u 0 0 1 special-reg etm0 etm1 v 0 0 1 special-reg ecnt ecpt p 2 0 0 0 0 1 p 1 0 0 1 1 0 p 0 0 1 0 1 0 reg-pair sp bc de hl ea q 2 0 0 0 0 1 q 1 0 0 1 1 0 q 0 0 1 0 1 0 reg-pair va bc de hl ea f 2 0 0 0 1 f 1 0 1 1 0 f 0 0 0 1 0 flag cy hc z sr3 sr4 rp rp1 f irf i 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 i 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 i 2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 i 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 i 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 intf nmi ft0 ft1 f1 f2 fe0 fe1 fein fad fsr fst er ov an4 an5 an6 an7 sb t 2 0 0 0 0 1 1 1 1 t 1 0 0 1 1 0 0 1 1 t 0 0 1 0 1 0 1 0 1 reg eah eal b c d e h l rpa a 2 0 0 0 0 1 1 1 1 0 1 1 1 1 a 1 0 0 1 1 0 0 1 1 1 0 0 1 1 a 0 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (bc) (de) (hl) (de)+ (hl)+ (de)- (hl)- (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) a 3 0 0 0 0 0 0 0 0 1 1 1 1 1 c 2 0 0 1 1 0 1 1 1 1 c 1 1 1 0 0 1 0 0 1 1 c 0 0 1 0 1 1 0 1 0 1 addressing (de) (hl) (de)++ (hl)++ (de + byte) (hl + a) (hl + b) (hl + ea) (hl + byte) c 3 0 0 0 0 1 1 1 1 1 rpa3 r r2 rpa rpa1 rpa2 sr sr1 sr2 rp rp2 rp3 22 m pd78c10a,78c11a,78c12a 4.3 instruction execution time 1 state shown here is composed of 3 clock cycles. when a clock cycle of 15 mhz is used, the execution time should be 200 ns (= 3 1/15 m s). in this case, the 4-state instruction which is the minimum execution time should be execution time of 0.8 m s. 23 m pd78c10a,78c11a,78c12a note 1. instruction group 2. 16-bit data transfer instructions note 1 mnemonic operand b1 b2 b3 b4 operation code state operation skip condition 8-bit data transfer instructions mov * * mvi r1, a a, r1 sr, a a, sr1 r, word word, r r, byte * sr2, byte mviw * wa, byte mvix rpa1, byte * staw * wa ldaw * wa stax * rpa2 ldax * rpa2 exx exa exh block dmov rp3, ea ea, rp3 00011t 2 t 1 t 0 00001t 2 t 1 t 0 01001101 01001100 01110000 01110000 01101r 2 r 1 r 0 01100100 01110001 010010a 1 a 0 01100011 00000001 a 3 0111a 2 a 1 a 0 a 3 0101a 2 a 1 a 0 00010001 00010000 01010000 00110001 101101p 1 p 0 101001p 1 p 0 11s 5 s 4 s 3 s 2 s 1 s 0 11s 5 s 4 s 3 s 2 s 1 s 0 01101r 2 r 1 r 0 01111r 2 r 1 r 0 data s 3 0000s 2 s 1 s 0 offset data offset offset data *1 data *1 low adrs low adrs data data high adrs high adrs r1 a a r1 sr a a sr1 r (word) (word) r 4 r byte sr2 byte (v. wa) byte (rpa1) byte (v. wa) a a (v. wa) (rpa2) a a (rpa2) b b', c c', d d' e e', h h', l l' v, a v', a', ea ea' (de) (hl) , c c ?1 end if borrow rp3 l eal, rp3 h eah eal rp3 l , eah rp3 h h, l h', l' 4 10 10 17 17 7 14 13 10 10 10 7/13 *3 7/13 *3 4 4 4 13 (c + 1) 4 4 note 2 ++ 24 m pd78c10a,78c11a,78c12a note 1. instruction group 2. 8-bit operation instructions (register) note 1 mnemonic operand b1 b2 b3 b4 operation code state operation skip condition 16-bit data transfer instructions dmov steax sr3, ea ea, sr4 word word word word rpa3 word lded word lhld word lspd word ldeax rpa3 push rp1 pop * rp1 lxi table add adc 01001000 01110000 01001000 10110q 2 q 1 q 0 10100q 2 q 1 q 0 0p 2 p 1 p 0 0100 01001000 01100000 00011110 00101110 00111110 00001110 data *2 low adrs low adrs high adrs high adrs sr3 ea (word) c, (word + 1) b (word) e, (word + 1) d (word) l, (word + 1) h (word) sp l , (word + 1) sp h (rpa3) eal, (rpa3 + 1) eah c (word), b (word + 1) e (word), d (word + 1) l (word), h (word + 1) sp l (word), sp h (word + 1) eal (rpa3), eah (rpa3 + 1) (sp ?1) rp1 h , (sp ?2) rp1 l rp2 word c (pc + 3 + a) 20 20 20 20 20 20 20 20 8 8 8 sbcd sded shld sspd lbcd rp2, word a, r r, a a, r r, a note 2 01110000 01001000 1101001u 0 1100000v 0 1001c 3 c 2 c 1 c 0 00011111 00101111 00111111 00001111 1000c 3 c 2 c 1 c 0 low byte 10101000 11000r 2 r 1 r 0 0100 1101 0101 data *2 high byte 14 14 14/20 13 10 10 17 8 sp sp ?2 b (pc + 3 + a + 1) a a + r r r + a a a + r + cy r r + a + cy rp1 l (sp), rp1 h (sp + 1) sp sp + 2 ea sr4 *3 14/20 *3 25 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition 8-bit operation instructions (register) addnc subnb a, r r, a a, r r, a a, r r, a a, r r, a ana a, r r, a ora a, r r, a xra a, r r, a gta lta nea 01100000 a a + r a a ?r r r ?a a a ?r ?cy r r ?a ?cy a a ?r r r ?a a a r 8 8 8 sub sbb a, r a, r r, a a, r r, a 10100r 2 r 1 r 0 0010 0011 1110 0110 8 a ?r r ?a r r + a r, a 1110 0110 1111 0111 1011 0011 10001r 2 r 1 r 0 0000 1001 0001 10010r 2 r 1 r 0 0001 10101 r 2 r 1 r 0 0010 1011 8 8 8 8 8 8 8 8 8 8 8 r r a a a r 8 8 8 8 8 r r a a a r r r a a ?r ?1 r ?a ?1 a ?r r ?a no carry no carry no borrow no borrow no zero no zero borrow borrow no borrow no borrow 26 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition 8-bit operation instructions (memory) eqa addncx a, r r, a a, r a, r rpa rpa rpa rpa sbbx rpa rpa anax rpa rpa xrax rpa rpa ltax eqax 01100000 a ?r a r a r a a + (rpa) a a + (rpa) a a ?(rpa) a a ?(rpa) ?cy offa addx rpa rpa 11111r 2 r 1 r 0 0111 1100 1101 a ?(rpa) a (rpa) r ?a rpa 1100 1101 1101 1010 1110 1011 1001 1110 1111 8 8 8 8 11 a a ?(rpa) a a (rpa) a a (rpa) a ?(rpa) a ?(rpa) a (rpa) zero zero no carry no borrow zero no zero zero no borrow ona adcx subx subnbx orax gtax neax onax offax 01110000 11000a 2 a 1 a 0 1111 10001a 2 a 1 a 0 10010a 2 a 1 a 0 10101a 2 a 1 a 0 1011 a a + (rpa) + cy 11 11 11 11 11 11 11 11 11 11 11 11 11 11 no zero zero borrow no zero 8-bit operation instructions (register) a ?(rpa) ?1 a a (rpa) rpa rpa 27 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition immediate data operation instructions aci * * adinc a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte * r, byte sr2, byte sui a, byte * r, byte sr2, byte sbi * suinb ani a, byte r, byte 01000110 01110100 0110 01010110 01110100 00100110 01110100 01100110 01110100 01110110 01110100 00110110 01110100 00000111 01110100 s 3 1000 s 2 s 1 s 0 01010r 2 r 1 r 0 data data data data a a + byte r r + byte sr2 sr2 + byte a a + byte + cy r r + byte + cy sr2 sr2 + byte + cy 7 a a + byte r r + byte sr2 sr2 + byte a a ?byte r r ?byte sr2 sr2 ?byte a a ?byte ?cy r r ?byte ?cy a a ?byte sr2 sr2 ?byte a a byte r r byte r r ?byte 20 11 20 7 11 20 11 20 7 7 adi a, byte r, byte sr2, byte a, byte r, byte sr2, byte 0110 0110 0110 0110 0110 data 01000r 2 r 1 r 0 data s 3 1010s 2 s 1 s 0 00100r 2 r 1 r 0 s 3 0100s 2 s 1 s 0 01100r 2 r 1 r 0 s 3 1100s 2 s 1 s 0 data 01110r 2 r 1 r 0 s 3 1110s 2 s 1 s 0 data 00110r 2 r 1 r 0 s 3 0110s 2 s 1 s 0 data data data data data 11 7 7 7 11 20 sr2 sr2 ?byte ?cy 11 20 no borrow no borrow no borrow no carry no carry no carry data * * 00001r 2 r 1 r 0 11 28 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition immediate data operation instructions * * gti a, byte r, byte sr2, byte a, byte r, byte sr2, byte a, byte * r, byte sr2, byte lti a, byte * r, byte sr2, byte nei * eqi 01100100 00010111 0110 00010110 01110100 00100111 01110100 00110111 01110100 01100111 01110100 01110111 01110100 00010r 2 r 1 r 0 data data data data a a byte r r byte sr2 sr2 byte a a byte r r byte sr2 sr2 byte a ?byte?1 r ?byte ?1 sr2 ?byte ?1 a ?byte r ?byte sr2 ?byte a ?byte sr2 ?byte r ?byte sr2 ?byte a ?byte 11 11 11 ori a, byte r, byte sr2, byte a, byte r, byte sr2, byte 0110 0110 0110 0110 0110 data data s 3 0010s 2 s 1 s 0 00101r 2 r 1 r 0 s 3 0101s 2 s 1 s 0 00111r 2 r 1 r 0 s 3 0111s 2 s 1 s 0 data 01101r 2 r 1 r 0 s 3 1101s 2 s 1 s 0 data 01111r 2 r 1 r 0 s 3 1111s 2 s 1 s 0 data data data 11 11 r ?byte 11 no zero data * ani sr2, byte xri zero 01110100 s 3 0001 s 2 s 1 s 0 00011r 2 r 1 r 0 s 3 0011 s 2 s 1 s 0 data 20 sr2 sr2 byte 7 20 7 20 7 14 7 14 7 14 7 14 zero zero no borrow no zero no zero borrow borrow borrow no borrow no borrow 29 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition working register operation instructions offi * * addw a, byte r, byte sr2, byte a, byte r, byte sr2, byte wa wa wa sbbw wa wa wa oraw ltaw eqaw wa wa 01000111 01110100 0110 01010111 01110100 01110100 s 3 1001 s 2 s 1 s 0 01011r 2 r 1 r 0 data offset a byte r byte sr2 byte a byte r byte sr2 byte 7 a a +(v. wa) a a + (v. wa) + cy a a + (v. wa) a a ?(v. wa) a a ?(v. wa) a a (v. wa) a a (v. wa) a ?(v. wa) a ?(v. wa) a (v. wa) a ?(v. wa) 14 11 14 14 14 14 14 oni wa wa wa wa wa wa 0110 data 01001r 2 r 1 r 0 data s 3 1011s 2 s 1 s 0 1101 data 11 7 14 14 14 14 borrow no borrow no borrow no carry immediate data operation instructions adcw addncw subw subnbw anaw xraw gtaw neaw onaw 11000000 1010 1110 1111 1011 10001000 1001 10010000 10101000 1011 1110 1111 1100 14 14 14 a a (v. wa) 14 14 14 a ?(v. wa) ?1 a a ?(v. wa) ?cy no zero no zero no zero zero zero zero no zero zero no zero 30 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition working register operation instructions ltiw * * eqiw wa wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte dadd ea, r2 ea, rp3 ea, rp3 esub dsubnb dor ea, rp3 ea, rp3 01110100 00000101 0001 data a (v. wa) (v. wa) (v. wa) byte (v. wa) (v. wa) byte (v. wa) ?byte ?1 (v. wa) ?byte (v. wa) ?byte (v. wa) ?byte (v. wa) byte (v. wa) byte ea ea + r2 ea ea + rp3 +cy ea ea + rp3 ea ea ?r2 ea ea rp3 ea ea rp3 ea ea rp3 ea ea ?rp3 19 13 13 13 13 11 11 offaw ea, rp3 ea, r2 ea, rp3 ea, rp3 ea, rp3 ea, rp3 0111 11011000 offset 19 11 11 11 11 borrow no borrow no borrow no carry oniw offiw eadd dadc daddnc dsub dsbb dan dxr 1101 1010 1111 1011 1001 13 11 11 ea ea ?rp3 11 11 11 ea ea ?rp3 ?cy ea ea + rp3 zero zero zero no zero aniw * oriw gtiw neiw * * * * 0010 0011 0100 0101 01110000 0100 0000 0100 010000r 1 r 0 110001p 1 p 0 011000r 1 r 0 111001p 1 p 0 100101p 1 p 0 100011p 1 p 0 0110 offset 14 13 no zero 16-bit operation instructions 31 m pd78c10a,78c11a,78c12a note 1. instruction group 2. multiplication/division instructions 3. other operation instructions note 1 mnemonic operand b1 b2 b3 b4 operation code state operation skip condition don mul ea, rp3 r2 inx wa rp ea dcrw daa clc 01110100 ea ?rp3 ?1 ea ?rp3 ea ?rp3 ea ?rp3 ea rp3 ea rp3 ea a r2 ea ea r2, r2 remainder r2 r2 + 1 (v. wa) (v. wa) + 1 ea ea + 1 r2 r2 ?1 (v. wa) (v. wa) ?1 cy 1 cy 0 a a + 1 decimal adjust accumulator 11 11 11 59 4 dgt r2 wa rp ea offset 11 16 borrow no borrow carry div inr inrw dcr dcx stc nega 32 16 rp rp ?1 ea ea ?1 rp rp + 1 zero zero no zero dlt dne deq doff * 00100000 001011r 1 r 0 00111010 11 11 16-bit operation instructions ea, rp3 ea, rp3 ea, rp3 ea, rp3 ea, rp3 r2 r2 01001000 010000r 1 r 0 00p 1 p 0 0010 10101000 010100r 1 r 0 00110000 00p 1 p 0 0011 10101001 01100001 01001000 101011p 1 p 0 1011 1110 1111 1100 1101 0011 offset 00101010 00101011 7 7 4 7 7 4 8 8 8 no zero carry borrow borrow note 2 increment/decrement instructions note 3 * 32 m pd78c10a,78c11a,78c12a note instruction group note mnemonic operand b1 b2 b3 b4 operation code state operation skip condition sll sllc r2 dsll ea ea ea jb jea calb 01001000 rotate left digit rotate right digit r2 m + 1 r2 m , r2 0 cy, cy r2 7 r2 m ?1 r2 m , r2 7 cy, cy r2 0 r2 m + 1 r2 m , r2 0 0, cy r2 7 r2 m ?1 r2 m , r2 7 0, cy r2 0 r2 m + 1 r2 m , r2 0 0, cy r2 7 r2 m ?1 r2 m , r2 7 0, cy r2 0 ea n + 1 ea n , ea 0 cy, cy ea 15 ea n ?1 ea n , ea 15 cy, cy ea 0 ea n ?1 ea n , ea 15 0, cy ea 0 pc word pc h b, pc l c pc ea 8 rld word 17 carry slrc drll drlr jmp jr call calf pc pc + 1 + jdisp 1 pc pc + 2 + jdisp ea n + 1 ea n , ea 0 0, cy ea 15 rrd rll rlr slr * 000001r 1 r 0 17 rotation/shift instructions r2 r2 r2 r2 r2 ea 01010100 00100001 11 0100111 01001000 01000000 00111000 low adrs 00101001 carry jump instructions call instructions dslr word jre word * * * word word 01001000 01111 jdisp 1 jdisp fa 00101000 low adrs 01r 1 r 0 1001 00r 1 r 0 001001r 1 r 0 00r 1 r 0 00r 1 r 0 10110100 0000 10100100 0000 high adrs high adrs 8 8 8 8 8 8 8 8 8 10 4 10 10 8 13 (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l pc word, sp sp ?2 pc h b, pc l c, sp sp ?2 (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l pc 15 ?11 00001, pc 10 ?0 fa, sp sp ?2 17 16 33 m pd78c10a,78c11a,78c12a *1. data is b2 if rpa2 = d + byte, h + byte. 2. data is b3 if rpa3 = d + byte, h + byte. 3. in the state item, a figure is in the right side of slash if rpa2 and rpa3 are d + byte, h + a, h + b, h + ea, h + byte. remarks the idle state when each instruction is skipped is different from the execution state as shown below. 1-byte instruction : 4 states 3-byte instruction (with *) : 10 states 2-byte instruction (with *) : 7 states 3-byte instruction : 11 states 2-byte instruction : 8 states 4-byte instruction : 14 states note 1. instruction group 2. call instructions note 1 mnemonic operand b1 b2 b3 b4 operation code state operation skip condition reti sk word f nop irf hlt 100 (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l pc l (sp), pc h (sp + 1) pc l (sp), pc h (sp + 1), sp sp +2 pc l (sp), pc h (sp + 1) skip if (v. wa) bit = 1 skip if f = 1 skip if f = 0 skip if irf = 1, then reset irf skip if irf = 0 enable interrupt disable interrupt set halt mode 10 13 10 8 calt offset 16 12 uncondi- tional skip f = 1 skn skit sknit di stop set stop mode no operation (v. wa)bit = 1 softi ret rets bit * 00001f 2 f 1 f 0 16 10 bit, wa f irf 01001000 00000000 10101010 10111010 01001000 01001000 0001 10111011 00111011 4 4 4 note 2 cpu control instructions ei 01110010 10111000 1001 01100010 01011b 2 b 1 b 0 ta 010i 4 i 3 i 2 i 1 i 0 011i 4 i 3 i 2 i 1 i 0 pc l (128 + 2ta), pc h (129 + 2ta), sp sp ?2 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc 0060h, sp sp ?3 reset irf, if irf = 1 8 8 8 12 sp sp + 2 pc pc + n psw (sp + 2), sp sp + 3 f = 0 irf = 1 irf = 0 return instructions skip instructions 34 m pd78c10a,78c11a,78c12a read/ name of mode registers function write ma mode a register w specifies bit-wise the input/output of the port a. mb mode b register w specifies bit-wise the input/output of the port b. mode control c register mc mode c register w specifies bit-wise the input/output of the port c which is in port mode. memory mapping register mf mode f register w specifies bit-wise the input/output of the port f which is in port mode. tmm timer mode register r/w specifies operating mode of timer. timer/event counter mode register timer/event counter output mode register sml w serial mode register specifies the operating mode of serial interface. smh r/w mkl interrupt mask register r/w specifies the enable/disable of the interrupt request. mkh a/d channel mode register zero-cross mode register 5. list of mode registers zcm w specifies the operation of zero-cross detector circuit. anm r/w specifies the operating mode of a/d converter. eom r/w control the output level of co0 and co1. etmm w specifies the operating mode of timer/event counter. mm w specifies the port/extension mode of port d and port f. mcc w specifies bit-wise the port/control mode of the port c. 35 m pd78c10a,78c11a,78c12a 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit v dd C0.5 to +7.0 v power supply voltage av dd av ss to v dd +0.5 v av ss C0.5 to +0.5 v input voltage v i C0.5 to v dd +0.5 v output voltage v o C0.5 to v dd +0.5 v all output pins 4.0 ma output current low total of all output pins 100 ma all output pins C2.0 ma output current high total of all output pins C50 ma a/d converter reference input voltage operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. i ol i oh v aref C0.5 to av dd +0.3 v h 36 m pd78c10a,78c11a,78c12a resonator recommended circuit parameter test conditions min. max. unit 5.8 15 mhz a/d converter not used x1 rise time, fall time (t r , t f ) x1 input high, low level width (t ? h , t ? l ) oscillator characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C0.8 v av dd v dd , 3.4 v v aref av dd ) 4 15 mhz maker product name csa7.37mt cst7.37mtw csa12.0mt cst12.0mtw csa15.00mx001 fcr8.0mc fcr10.0mc fcr12.0omc fcr15.0mc recommended constants c1[pf] 30 on-chip 30 on-chip 15 on-chip c2[pf] 30 on-chip 30 on-chip 15 on-chip murata mfg. co., ltd tdk corp. *2. when a crystal oscillator is used, the following external capacitance is recommended. c1 = c2 = 10 pf a/d converter not used a/d converter used oscillator frequency (f xx ) x1 input frequency (f x ) cautions 1. place oscillator circuit as close as possible to x1, x2 pins. 2. ensure that no other signal lines pass through the shadow area. 020ns 20 250 ns a/d converter used 5.8 15 mhz 4 15 mhz external clock ceramic *1 or crystal resonator *2 *1. the ceramic oscillators and external capacitance given in the following table are recommended. x1 x2 c2 c1 x1 x2 hcmos inverter 37 m pd78c10a,78c11a,78c12a capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i 10 pf f c = 1 mhz output capacitance c o 20 pf unmeasured pins returned to 0 v input-output capacitance c io 20 pf 38 m pd78c10a,78c11a,78c12a dc characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) parameter symbol test conditions min. typ. max. unit all except reset, stop, nmi, sck, int1, ti, an4 to an7 reset, stop, nmi, sck, int1, ti, an4 to an7 all except reset, stop, nmi, sck, int1, ti, an4 to an7, x1, x2 reset, stop, nmi, sck, int1, ti, an4 to an7, x1, x2 output voltage low v ol i ol = 2.0 ma 0.45 v v dd v C1.0 v dd v C0.5 input current i i int1 *1 , ti(pc3) *2 ; 0 v v i v dd 200 m a all except int1, ti (pc3), 10 m a 0 v v i v dd output leakage 10 m a current ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma ai dd2 stop mode 10 20 m a i dd1 operating mode f xx = 15 mhz 13 25 ma i dd2 halt mode f xx = 15 mhz 7 13 ma data retention hardware/software stop mode 2.5 v voltage hardware/software *3 v dddr = 2.5 v 1 15 m a stop mode v dddr = 5 v 10% 10 50 m a pull-up resistor *4 ports a, b and c 3.5 v v dd 5.5 v, 17 27 75 k w v i = 0 v caution for a detailed description of the hardware stop mode, refer to the 87ad series m pd78c18 user's manual. *1. if self-bias should be generated by zcm register. 2. if the control mode is set by mcc register, and self-bias should be generated by zcm register. 3. if self-bias is not generated. 4. m pd78c11a and 78c12a only. input voltage low input voltage high output voltage high input leakage current av dd power supply current v dd power supply current data retention current v il2 i li i lo v il1 v 1ih v ih2 v oh 0 v v o v dd r l i dddr v dddr 0 0.2 v dd v 0 0.8 v 2.2 v dd v i oh = C1.0 ma i oh = C100 m a 0.8 v dd v dd v 39 m pd78c10a,78c11a,78c12a ac characteristics (t a = C40 to +85 c, v dd = av dd = +5.0 v 10 %, v ss = av ss = 0 v) read/write operation: f xx = 15 mhz, c l = 100 pf rd low level width t rr f xx = 15 mhz f xx = 15 mhz, c l = 100 pf parameter symbol test conditions min. max. unit x1 input cycle time t cyc 66 250 ns address setup time (to ale ? )t al 30 ns address hold time (from ale ? )t la f xx = 15 mhz, cl = 100 pf 35 ns rd ? delay time from address t ar 100 ns address float time from rd ? t afr c l = 100 pf 20 ns data input time from address t ad 250 ns data input time from ale ? t ldr 135 ns data input time from rd ? t rd 120 ns rd ? delay time from ale ? t lr 15 ns data hold time (from rd )t rdh c l = 100 pf 0 ns ale delay time from rd t rl f xx = 15 mhz, c l = 100 pf 80 ns in data read 215 ns f xx = 15 mhz, c l = 100 pf in op code fetch 415 ns f xx = 15 mhz, c l = 100 pf ale high level width t ll f xx = 15 mhz, c l = 100 pf 90 ns m1 setup time (to ale ? )t ml 30 ns m1 hold time (from ale ? )t lm 35 ns io/m setup time (to ale ? )t il 30 ns io/m hold time (from ale ? )t li 35 ns t aw 100 ns data output time from ale ? t ldw 180 ns data output time from wr ? t wd c l = 100 pf 100 ns wr ? delay time from ale ? t lw 15 ns data setup time (to wr )t dw 165 ns data hold time (from wr )t wdh f xx = 15 mhz, c l = 100 pf 60 ns ale delay time from wr t wl 80 ns wr low level width t ww 215 ns wr ? delay time from address 40 m pd78c10a,78c11a,78c12a parameter symbol test conditions min. max. unit sck input *1 800 ns *2 400 ns sck output 1.6 m s sck input *1 335 ns *2 160 ns sck output 700 ns sck input *1 335 ns *2 160 ns sck output 700 ns r x d setup time (to sck )t rxk *1 80 ns r x d hold time (from sck )t krx *1 80 ns t x d delay time from sck ? t ktx *1 210 ns serial operation : *1. if clock rate is 1 in asynchronous mode, synchronous mode, or i/o interface mode. 2. if clock rate is 16 or 64 in asynchronous mode. remarks the numeric values in the table are those when f xx = 15 mhz, c l = 100 pf. zero-cross characteristics : parameter symbol test conditions min. max. unit zero-cross detection input v zx 1 1.8 vac p-p zero-cross accuracy a zx 135 mv zero-cross detection input 0.05 1 khz frequency other operation : parameter symbol test conditions min. max. unit ti high, low level width t tih , t til 6t cyc ci high, low level width t ci1h , t ci1l event count mode 6 t cyc t ci2h ,t ci2l pulse width test mode 48 t cyc nmi high, low level width t nih , t nil 10 m s int1 high, low level width t i1h , t i1l 36 t cyc int2 high, low level width t i2h , t i2l 36 t cyc an4 to an7, low level width t anh , t anl 36 t cyc reset high, low level width t rsh , t rsl 10 m s sck cycle time t cyk sck low level width t kkl sck high level width t kkh f zx ac combination 60 hz sine wave 41 m pd78c10a,78c11a,78c12a a/d converter characteristics (t a = C40 to +85 c, v dd = +5.0 v 10 %, v ss = av ss = 0 v, v dd C0.5 v av dd v dd , 3.4 v v aref av dd ) parameter symbol test conditions min. typ. max. unit resolution 8 bits 3.4 v v aref av dd , 66 ns t cyc 170 ns 0.8% fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns 0.6% fsr t a = C10 to +70 c, 0.4% fsr 4.0 v v aref av dd , 66 ns t cyc 170 ns 66 ns t cyc 110 ns 576 t cyc 110 ns t cyc 170 ns 432 t cyc 66 ns t cyc 110 ns 96 t cyc 110 ns t cyc 170 ns 72 t cyc analog input voltage v ian an0 to an7 (including unused pins) C0.3 v aref +0.3 v analog input 50 m w impedance reference voltage v aref 3.4 av dd v i aref1 operating mode 1.5 3.0 ma i aref2 stop mode 0.7 1.5 ma ai dd1 operating mode f xx = 15 mhz 0.5 1.3 ma ai dd2 stop mode 10 20 m a * quantization error ( 1/2 lsb) is not included. ac timing test point 2.2 v 0.8 v 2.2 v 0.8 v test points v dd ?1.0 v 0.45 v r an absolute accuracy * conversion time t conv sampling time t samp v aref current av dd power supply current h 42 m pd78c10a,78c11a,78c12a t cyc -dependent ac characteristics expression t cyk t kkl t kkh t rr parameter expression min./max. unit t al 2t C 100 min. ns t la t C 30 min. ns t ar 3t C 100 min. ns t ad 7t C 220 max. ns t ldr 5t C 200 max. ns t rd 4t C 150 max. ns t lr t C 50 min. ns t rl 2t C 50 min. ns 4t C 50 (in data read) min. ns 7t C 50 (in op code fetch) t ll 2t C 40 min. ns t ml 2t C 100 min. ns t lm t C 30 min. ns t il 2t C 100 min. ns t li t C 30 min. ns t aw 3t C 100 min. ns t ldw t + 110 max. ns t lw t C 50 min. ns t dw 4t C 100 min. ns t wdh 2t C 70 min. ns t wl 2t C 50 min. ns t ww 4t C 50 min. ns 12t (sck input) *1 /6t (sck input) *2 min. ns 24t (sck output) 5t + 5 (sck input) *1 /2.5t + 5 (sck input) *2 min. ns 12t C 100 (sck output) 5t + 5 (sck input) *1 /2.5t + 5 (sck input) *2 min. ns 12t C 100 (sck output) *1. if clock rate is 1, in asynchronous mode, synchronous mode, or i/o interface mode. 2. if clock rate is 16 64, in asynchronous mode. cautions 1. t = tcyc = 1/fxx 2. other items which are not listed in this table are not dependent on oscillator frequency (fxx). 43 m pd78c10a,78c11a,78c12a timing waveform read operation *1. when mode1 pin is pulled up, m1 signal is output to mode1 pin in the 1st op code fetch cycle. 2. when mode0 pin is pulled up, io/m signal is output to mode0 pin in sr to sr2 register read cycle. write operation *3. when mode0 pin is pulled up, io/m signal is output to mode0 pin in sr to sr2 register write cycle. x1 pf7 - 0 pd7 - 0 ale mode1 (m1) *1 mode0 (io/m) *2 t cyc address (upper) address (lower) t rdh read data t ldr t ad t rl t rd t rr t afr t la t ll t ar t al t lr t ml t il t lm t li address (upper) address (lower) t ldw t la t ll t al t wd t dw t wdh t wl t ww t lw t li t aw t il write data x1 pf7 - 0 pd7 - 0 ale rd wr mode0 (io/m) *3 44 m pd78c10a,78c11a,78c12a serial operation timer/event counter input timing timer input timing t cyk t kkl t kkh t rxk t krx t ktx sck t x d r x d ti t til t tih ci t ci1l t ci1h event counter mode ci t ci2l t ci2h pulse width test mode 45 m pd78c10a,78c11a,78c12a interrupt input timing external clock timing reset t rsl t rsh 0.8 v dd 0.2 v dd reset input timing nmi t nil t nih int1 int2 t i1h t i1l t i2l t i2h x1 t cyc 0.8 v dd 0.8 v t f t r t h f t h f 46 m pd78c10a,78c11a,78c12a data memory stop mode low power supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention power 2.5 5.5 v supply voltage v dddr = 2.5 v 1 15 m a v dddr = 5 v 10% 10 50 m a v dd rise/fall time t rvd , t fvd 200 m s stop setup time 12t +0.5 m s (to v dd ) stop hold time 12t +0.5 m s (from v dd ) data retention timing 90 % stop v dd v dddr t rvd 10 % t fvd t sstvd t hvdst v ih2 v il2 v dddr t sstvd t hvdst data retention power supply current i dddr h 47 m pd78c10a,78c11a,78c12a i dd1 , i dd2 vs f xx 7. characteristic curves (reference values) i dd1 , i dd2 vs v dd 20 15 10 5 0 4.5 5.0 5.5 (t a = 25 ?c, f xx = 15 mhz) i dd1 (typ.) i dd2 (typ.) power supply voltage v dd [v] v dd power supply current i dd1 , i dd2 [ma] (t a = 25 ?c, v dd = 5 v) oscillator frequency f xx [mhz] v dd power supply current i dd1 , i dd2 [ma] 30 20 10 0 5 10 15 i dd1 (typ.) i dd2 (typ.) 6 48 m pd78c10a,78c11a,78c12a i ol vs v ol i oh vs v oh 2.5 2.0 1.5 1.0 0.5 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) typ. output voltage low v ol [v] output current low i ol [ma] ?.5 ?.0 ?.5 0 0.1 0.2 0.3 0.4 0.5 (t a = 25 ?c, v dd = 5 v) power supply voltage ?output voltage high v dd ?v oh [v] output current high i oh [ma] typ. 49 m pd78c10a,78c11a,78c12a i dddr vs v dddr 10 8 6 4 2 0 2 3456 (t a = 25 ?c) typ. data retention power supply voltage v dddr [v] data retention power supply current i dddr [ a] m 50 m pd78c10a,78c11a,78c12a i aref2 8. differences in 87ad series products (1/2) item 159 kinds (stop instruction added) 158 kinds number of instructions m pd7810, 7811 *1 m pd7810h, 7811h m pd78c10, 78c11 *1 product name on-chip ram 256 8 bits nnmber of special registers 27 28 (zcm register added) operating frequency power supply voltage operating temperature range standby function thirty-two bytes of the on-chip ram 256 bytes of data are held by low power supply voltage (3.2 v) number of halt instruction state 11 12 halt mode cpu operation ale m3 t2 cycle repeated high level stop low level zero crossing detector self-bias control self-bias control impossible nmi, reset noise elimination method by clock sampling by analog delay operation stop possible (v aref pin operation) operation stop impossible a/d converter operation control 0.4% (t a = C10 to +70 c, v aref = 4.0v to av dd ) 0.6% (t a = C40 to +85 c, v aref = 4.0v to av dd ) 0.8% (t a = C40 to +85 c v aref = 3.4v to av dd ) a/d converter absolute accuracy (unit: fsr) v aref voltage range av cc to 0.5v to av cc 3.4 v to av dd ai cc /ai dd1 0v to v aref analog input voltage range 6 ma typ. 0.5 ma typ. ai dd2 10 m a typ. i aref /i aref1 0.5 ma typ. 2.0 ma typ. 1.5 ma typ. 0.7 ma typ. 0.4% (t a = C10 to +50 c) 0.6% (t a = C40 to +85 c) three kinds: halt mode, software stop mode, and hardware stop mode. all data of on-chip ram are held by low power supply voltage (2.5v) in software/ hardware stop mode. 0.4% (t a = C10 to +70 c) *3 10 to 12 mhz 5 v 5 % C10 to +70 c 4 to 10 mhz 5 v 10 % C40 to +85 c 4 to 15 mhz 5 v 10 % C10 to +70 c 4 to 15 mhz *2 5 v 10 % C40 to +85 c self-bias control possible (by zcm register specification) *1. m pd7810, 7811, 78c10 and 78c11 are maintenance products. 2 . k, e, p masks apply from 4 mhz to 12 mhz. 3. the m pd7810hg and 7811hg g masks, m pd7810hcw and 7811hcw k masks apply t a = 0 to +70 c. on-chip rom rom less ( m pd7810) 4k 8 bits ( m pd7811) rom less ( m pd7810h) 4k 8 bits ( m pd7811h) rom less ( m pd78c10) 4k 8 bits ( m pd78c11) 51 m pd78c10a,78c11a,78c12a 4 to 15 mhz 5 v 10 % C40 to +85 c 6 to 15 mhz 5 v 5 % C40 to +85 c 4 to 15 mhz 5 v 10 % C40 to +85 c 0.7 ma typ. m pd78c10a, 78c11a, 78c12a m pd78cp14 m pd78cp18 3.4v to av dd C0.3 v to v aref + 0.3 v 0v to v aref C0.3 v to v aref + 0.3 v 1.5 ma typ. 10 m a typ. 0.5ma typ. self-bias control possible (by zcm register specification) 12 stop low level 28 (zcm register added) 256 8 bits 1024 8 bits 159 kinds (stop instruction added) operation stop impossible (v aref pin operation) by analog delay three kinds: halt mode, software stop mode, and hardware stop mode. all data of on-chip ram are held by low power supply voltage (2.5 v) in software/hardware stop mode. 0.4% (t a = C10 to +70 c, v aref = 4.0 v to av dd ) 0.6% (t a = C40 to +85 c, v aref = 4.0 v to av dd ) 0.8% (t a = C40 to +85 c, v aref = 3.4 v to av dd ) 32k 8 bits (prom) 16k 8 bits (prom) rom less ( m pd78c10a) 4k 8 bits ( m pd78c11a) 8k 8 bits ( m pd78c12a) 52 m pd78c10a,78c11a,78c12a 20t 10t + 80 10t C 80 item m pd7810, 7811 *1 m pd7810h, 7811h m pd78c10, 78c11 *1 differences in 87ad series products (2/2) zero is output at the pin specified by the address bus. other pins are high impedance. impossible on-chip pull-up register (mask option) device configuration nmos cmos 3.2 ma (C10 to +70 c) max. 3.5 ma (C40 to +85 c) max. standby current current consumption cycle time input low level width high level width *5 sck (unit: ns) t ldw t wd t dw bus timing (unit: ns) t + 110 100 4t C 100 hardware stop mode restrictions yes asyncronous mode restrictions during external sck input. no yes 64-pin plastic shrink dip 64-pin plastic quip straight *8 64-pin plastic quip 64-pin plastic qfp (14 20 mm, 2.05 mm thickness) 64-pin plastic qfp (14 20 mm, 2.70 mm thickness) 68-pin plastic qfj package pin connection *10 v cc (64-pin), v dd (63-pin) v dd (64-pin), stop (63-pin) rd/wr ale pd/pf *4 high-impedance *1. m pd7810, 7811, 78c10 and 78c11 are maintenance products. 4 . for m pd7810, 7810h, 78c10 and 78c10a. 5. for the asyncronous mode with clock rate x1, syncronous mode, and i/o interface mode for the asyncronous mode with clock rate 16 and 64 cycle time input low level width high level width sck 12t 5t + 5 5t + 5 6t 2.5t + 5 2.5t + 5 remarks t = t cyc = 1/f xx 203.2 ma (C10 to +70 c) max. 223.5 ma (C40 to +85 c) max. operation during reset product name (unit : ns) 64-pin plastic shrink dip 64-pin plastic quip straight *7 64-pin plastic quip output high level 3.2 ma max. 50 m a max. (v dd = 5 v 10 %) 203.2 ma max. 25 ma max. h 53 m pd78c10a,78c11a,78c12a cmos m pd78c10a, 78c11a, 78c12a m pd78cp14 m pd78cp18 64-pin plastic shrink dip 64-pin plastic quip 64-pin plastic qfp (14 20 mm, 2.70 mm thickness) 68-pin plastic qfj 64-pin ceramic shrink dip with window 64-pin ceramic quip with window 64-pin ceramic wqfn t + 110 t + 130 110 140 4t C 100 4t C 140 yes *6 no only m pd78c11a, 78c12a possible (ports a, b, c) impossible high-impedance *5 no 64-pin plastic shrink dip 64-pin plastic quip straight *9 64-pin plastic quip 64-pin plastic qfp (14 20 mm, 2.70 mm thickness) 68-pin plastic qfj 64-pin plastic shrink dip 64-pin plastic quip 64-pin plastic qfp (14 20 mm, 2.70 mm thickness) 64-pin ceramic shrink dip with window 64-pin ceramic wqfn 1 ma max. (v dd = 5 v 5 %) 50 m a max. (v dd = 5 v 10 %) 25 ma max. 32 ma max. 35 ma max. 50 m a max. (v dd = 5 v 10 %) v dd (64-pin), stop (63-pin) *6. k mask products only 7. m pd7811, 7811h only 8. m pd78c11, only 9. m pd78c11a, 78c12a only 10. items in the parentheses are the pin numbers for the 64-pin plastic shrink dip, 64-pin plastic quip straight and 64-pin plastic quip. caution since the oscillator characteristics, i/o level, and some internal operation timing are different, be careful when studying direct replacement of the m pd78c10a, 78c11a, 78c12a and m pd7810, 7811, 7810h, 7811h, 78c10, 78c11. h 54 m pd78c10a,78c11a,78c12a a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil) 9. package information 55 m pd78c10a,78c11a,78c12a 56 m pd78c10a,78c11a,78c12a 57 m pd78c10a,78c11a,78c12a 64pin plastic qfp (14 20) (unit: mm) n a m f b 51 52 32 k l 64 1 20 19 33 p d c detail of lead end s q 55 g m i h j p64gf-100-3b8,3be,3br-1 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 1.0 0.40 0.10 0.20 20.0 0.2 0.929 0.016 0.039 0.039 0.008 0.039 (t.p.) 0.795 note m n 0.12 0.15 1.8 0.2 1.0 (t.p.) 0.005 0.006 +0.004 ?.003 each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 0.071 0.016 0.551 0.8 0.2 0.031 p 2.7 0.106 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.008 ?.009 58 m pd78c10a,78c11a,78c12a es 64pin ceramic qfp (reference drawing) (unit: mm) cautions 1. the metal cap is connected to pin 26 and is v ss (gnd) level. 2. the bottom leads are tilted. 3. since cutting of the end of the leads is no process-controlled, the lead length is unspecified. 59 m pd78c10a,78c11a,78c12a 68pin plastic qfj ( 950 mil) (unit: mm) p68l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 1.0 0.12 23.12 0.20 0.15 r 0.8 0.20 +0.10 ?.05 0.992 0.008 0.953 0.953 0.992 0.008 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.910 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005 +0.004 ?.002 +0.009 ?.008 n k m q a u 68 b d c 1 f e t p m g h ij 60 m pd78c10a, 78c11a, 78c12a h 10. recommended soldering conditions the m pd78c10a, 78c11a, and 78c12a should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document "semiconductor device mounting technology manual" (iei-1207). for soldering methods and conditions other than those recommended below, contact our sales personnel. table 10-1 surface mounting type soldering conditions (1) m pd78c10agf-3be : 64-pin plastic qfp (14 20 mm) m pd78c11agf- -3be : 64-pin plastic qfp (14 20 mm) m pd78c12agf- -3be : 64-pin plastic qfp (14 20 mm) soldering conditions soldering method infrared reflow package peak temperature : 235 c, duration : 30 sec. max. (210 c min.), number of times : 2 max. 61 m pd78c10a, 78c11a, 78c12a table 10-2 inserted type soldering conditions (1) m pd78c10acw : 64-pin plastic shrink dip (750 mil) m pd78c11acw- : 64-pin plastic shrink dip (750 mil) m pd78c12acw- : 64-pin plastic shrink dip (750 mil) m pd78c10agq-36 : 64-pin plastic quip m pd78c11agq- -36 : 64-pin plastic quip m pd78c12agq- -36 : 64-pin plastic quip soldering method soldering conditions wave soldering (pin only) solder bath temperature: 260 c max. duration: 10 sec. max. pin part heating pin temperature: 300 c max. duration: 3 sec. max. (per pin) caution ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly. (2) m pd78c11agq- -37 : 64-pin plastic quip straight m pd78c12agq- -37 : 64-pin plastic quip straight soldering conditions pin temperature: 300 c max. duration: 3 sec. max. (per pin) pin part heating soldering method 62 m pd78c10a,78c11a,78c12a appendix development tools the following development tools are available to develop a system which uses 87ad series products. language processor supply medium os ms-dos ver. 2.11 to ver. 5.00a* pc dos (ver. 3.1) software hardware supply medium this is a program which converts a program written in mnemonic to an object code that micro- computer execution is possible. besides, it contains a function to automatically create a symbol/table, and optimize a branch instruction. 87ad series relocatable assembler (ra87) pc-9800 series ibm pc/at tm m s5a13ra87 m s5a10ra87 ordering code (product name) host machine with an provided board and an optional programmer adapter connected, this prom programmer can manipulate from a stand-alone or host machine to perform programming on single-chip microcomputer which incorporates prom. it is also capable of programming a typical prom ranging from 256k to 4m bits. pg-1500 pa-78cp14cw/ gf/gq/kb/l pa-78cp14cw pa-78cp14gf pa-78cp14gq pa-78cp14kb pa-78cp14l prom programmer adapter for m pd78cp14/78cp18. used by connecting to pg-1500. for m pd78cp14cw, 78cp14dw, 78cp18cw, 78cp18dw for m pd78cp14gf-3be, 78cp18gf-3be for m pd78cp14g-36, 78cp14r, 78cp18gq-36 for m pd78cp14kb, 78cp18kb for m pd78cp14l connected pg-1500 to a host machine by using serial and parallel interface, to control the pg- 1500 on a host machine. pc-9800 series ibm pc/at host machine m s5a13pg1500 m s5a10pg1500 m s7b10pg1500 ordering code (product name) 3.5-inch 2hd 5-inch 2hc pg-1500 controller h 3.5-inch 2hd 5-inch 2hd 5-inch 2hd m s7b13ra87 m s7b10ra87 3.5-inch 2hc 5-inch 2hc * ver. 5.00/5.00a has a task swap function, but this function cannot be used with this software. remarks operation of assemblers and the pg-1500 controller are guaranteed only on the host machines and operating systems quoted above. os ms-dos tm ver. 2.11 to ver. 5.00a* pc dos tm (ver. 3.1) prom write tools 63 m pd78c10a,78c11a,78c12a os ms-dos ver. 2.11 to ver. 3.30d pc dos (ver. 3.1) debugging tools an in-circuit emulator (ie-78c11-m) is available as a program debugging tool for 87ad series. the following table shows its system configuration. the ie-78c11-m is an in-circuit emulator which works with 87ad series. only the ie-78c11-m should be used for a plastic quip package, while it should be used with a conversion socket for a plastic shrink dip package. it can be connected to a host machine to perform efficient debugging. conversion sockets for plastic shrink dip. used in combination with the ie-78c11-m. 64-pin lcc socket. can be used as a substitute for 64-pin plastic qfp products with window in combination with the m pd78cp14kb/78cp18kb. connects the ie-78c11-m to host machine by using the rs-232-c, then controls the ie-78c11-m on host machine. hardware supply medium software remarks operation of the ie controller is guaranteed only on the host machine and operating systems quoted above. ie-78c11-m ev-9001-64 ev-9200g-64 ie-78c11-m control program (ie controller) pc-9800 series ibm pc/at host machine m s5a13ie78c11 m s5a10ie78c11 m s7b10ie78c11 ordering code (product name) 5-inch 2hd 3.5-inch 2hd 5-inch 2hc 64 m pd78c10a,78c11a,78c12a [memo] 65 m pd78c10a,78c11a,78c12a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 ms-dos is a trademark of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. the customer must judge : m pd78c11acw- , 78c11agf- -3be, 78c11agq- -36, 78c11agq- -37, the need for license m pd78c11al- , 78c12acw- , 78c12agf- -3be, 78c12agq- -36, m pd78c12agq- -37, 78c12al- license not needed : m pd78c10acw, 78c10agf-3be, 78c10agq-36, 78c10al the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m pd78c10a,78c11a,78c12a |
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